Paresh Patel

Paresh Patel

President & CEO, System Level Solutions, Inc.

Mr. Paresh Patel is the Founder of System Level Solutions, Inc., USA and Managing Director of System Level Solutions (India) Pvt. Ltd. a wholly owned subsidiary of System Level Solutions, Inc., USA. For System Level Solutions he manages India and USA operations, which includes a staff of 200+ engineering professionals responsible for FPGA design, Intellectual Property, PCB Development, OS porting, Software applications and drivers for Windows as well as Linux. In addition, he drives product planning and development for a number of SLS products as well as OEM products for customers around the world.

Prior to System Level Solutions, Mr. Patel was the Director of ASIC Development at Eclipse International, Inc. He built the entire ASIC capability from the ground up and within one year delivered first silicon success of a companion chip for Hitachi SH3 processors for use in Windows CE handheld devices. Following the success of the first chip, three more ICs were developed which worked with Hitachi, NEC and Intel StrongArm processors. Furthermore, he architected a FPGA based prototype development system and managed the PCB development and necessary software tools in order to ensure first silicon success.

Prior to Eclipse International, Mr. Paresh Patel worked as a consultant at Intel simulating various functional blocks for the Itanium chip.

Prior to consulting at Intel, Mr. Patel worked as a Design Engineer at Hitachi Semiconductor (USA) Corp and Hitachi Micro Systems, Inc. He worked on all aspects of IC design. This included library characterization using SPICE, placement, routing, test vector generation, synthesis, and simulation. During his tenure at Hitachi Semiconductor, Mr. Patel successfully released 5 Gate Array designs and 2 ASIC designs. At Hitachi Micro Systems Inc., Mr. Patel oversaw the development of a cutting edge floor planning tool written in C for internal IC development.

Mr. Patel earned his Bachelor’s degree (B.S.E.E. 1991 Cum Laude) from Santa Clara University with specialization in Analog and Digital Systems and later his Master’s degree (M.S.E.E. 1993) from Santa Clara University with specialization in Microelectronics. As part of his Master’s thesis, he worked at Xerox Palo Alto Research Center (PARC) perfecting in-situ pulsed laser deposition of superconductors on silicon substrates. He has presented and published a number of papers relating to YBCO (superconductor) on Yttria Stablized Zirconia.